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PLUS405-37/-45 programmable logic sequencers (16 64 8) product specification 1996 nov 12 integrated circuits ic13 data handbook
philips semiconductors product specification PLUS405-37/-45 programmable logic sequencers (16 64 8) 2 1996 nov 12 8531280 17500 description the plus405 devices are bipolar , programmable state machines of the mealy type. both the and and the or array are user-programmable. all 64 and gates are connected to the 16 external dedicated inputs (i0 - i15) and to the feedback paths of the 8 on-chip state registers (q p0 - q p7 ). two complement arrays support complex if-then-else state transitions with a single product term (input variables c0, c1) . all state transition terms can include t rue, false and don't care states of the controlling state variables. all and gates are merged into the programmable or array to issue the next-state and next-output commands to their respective registers. because the or array is programmable, any one or all of the 64 transition terms can be connected to any or all of the state and output registers. all state (q p0 - q p7 ) and output (q f0 - q f7 ) registers are edge-triggered, clocked j-k flip-flops, with asynchronous preset and reset options. the plus405 architecture provides the added flexibility of the j-k toggle function which is indeterminate on s-r flip-flops. each register may be individually programmed such that a specific preset-reset pattern is initialized when the initialization pin is raised to a logic level a1o. this feature allows the state machine to be asynchronously initialized to known internal state and output conditions, prior to proceeding through a sequence of state transitions. upon power-up, all registers are unconditionally preset to a1o. if desired, the initialization input pin (init) can be converted to an output enable (oe ) function as an additional user-programmable feature. a vailability of two user-programmable clocks allows the user to design two independently clocked state machine functions consisting of four state and four output bits each. order codes are listed in the ordering information t able. features ? PLUS405-37 f max = 37mhz 50mhz clock rate ? plus405-45 f max = 45mhz 58.8mhz clock rate ? functional superset of pls105/105a ? field-programmable (ti-w fusible link) ? 16 input variables ? 8 output functions ? 64 transition terms ? 8-bit state register ? 8-bit output register ? 2 transition complement arrays ? multiple clocks* ? programmable asynchronous initialization or output enable ? power-on preset of all registers to a1o ? aon-chipo diagnostic test mode features for access to state and output registers ? 950mw power dissipation (typ.) ? ttl compatible ? j-k or s-r flip-flop functions ? automatic aholdo states ? 3-state outputs applications ? interface protocols ? sequence detectors ? peripheral controllers ? timing generators ? sequential circuits ? elevator contollers ? security locking systems ? counters ? shift registers pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 n package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 clk i7 i6 i5/clk i4 i3 i2 i1 i0 f7 f6 f5 f4 gnd f3 f2 f1 f0 init/oe i15 i14 i13 i12 i11 i10 i9 i8 v cc clk i6 i7 v cc i5/clk i8 i9 i4 i3 i2 i1 i0 f7 f6 f5 f4 gnd f3 f2 f1 f0 init/oe i15 i14 i13 i12 i11 i10 n = plastic dip (600mil-wide) a = plastic leaded chip carrier a package sp00251
philips semiconductors product specification PLUS405-37/-45 programmable logic sequencers (16 64 8) 1996 nov 12 3 ordering information description operating frequency order code drawing number 28-pin plastic dip (600mil-wide) 45mhz (t is1 + t cko1 ) plus40545n sot117-2 28-pin plastic dip (600mil-wide) 37mhz (t is1 + t cko1 ) plus40537n sot117-2 28-pin plastic leaded chip carrier 45mhz (t is1 + t cko1 ) plus40545a sot261-3 28-pin plastic leaded chip carrier 37mhz (t is1 + t cko1 ) plus40537a sot261-3 pin description pin no. symbol name and function polarity 1 clk1 clock: the clock input to the state and output registers. a low-to-high transition on this line is necessary to update the contents of both state and output registers. pin 1 only clocks p03 and f03 if pin 4 is also being used as a clock. active-high (h) 2, 3, 59, 2627 2022 i0i4, i7, i6 i8i9 i13i15 logic inputs: the 12 external inputs to the and array used to program jump conditions between machine states, as determined by a given logic sequence. t rue and complement signals are generated via use of aho and alo. active-high/low (h/l) 4 clk2 logic input/clock: a user programmable function: ? logic input: a 13th external logic input to the and array , as above. active-high/low (h/l) ? clock: a 2nd clock for the state registers p47 and output registers f47, as above. note that input buffer i 5 must be deleted from the and array (i.e., all fuse locations adon't careo) when using pin 4 as a clock. active-high (h) 23 i12 logic/diagnostic input: a 14th external logic input to the and array , as above, when exercising standard ttl or cmos levels. when i12 is held at +10v , device outputs f0f7 reflect the contents of state register bits p0p7. the contents of each output register remains unaltered. active-high/low (h/l) 24 i11 logic/diagnostic input: a 15th external logic input to the and array , as above, when exercising standard ttl levels. when i11 is held at +10v, device outputs f0f7 become direct inputs for state register bits p0p7; a low-to-high transition on the appropriate clock line loads the values on pins f0f7 into the state register bits p0p7. the contents of each output register remains unaltered. active-high/low (h/l) 25 i10 logic/diagnostic input: a 16th external logic input to the and array , as above, when exercising standard ttl levels. when i 10 is held at +10v, device outputs f0f7 become direct inputs for output register bits q0q7; a low-to-high transition on the appropriate clock line loads the values on pins f0f7 into the output register bits q0q7. the con - tents of each state register remains unaltered. active-high/low (h/l) 1013 1518 f0 f7 logic outputs/diagnostic outputs/diagnostic inputs: eight device outputs which nor- mally reflect the contents of output register bits q0q7, when enabled. when i12 is held at +10v, f0f7 = (p0p7). when i11 is held at +10v , f0f7 become inputs to state reg - ister bits p0p7. when i10 is held at +10v , f0f7 become inputs to output register bits q0q7. active-high (h) 19 init/oe initialization or output enable input: a user programmable function: ? initialization: provides an asynchronous preset to logic a1o or reset to logic a0o of all state and output register bits, determined individually for each register bit through user programming. init overrides clock, and when held high, clocking is inhibited and f0f7 and p0p7 are in their initialization state. normal clocking resumes with the first full clock pulse following a high-to-low clock transition, after init goes low . see timing definition for t nvck and t vck . active-high (h) ? output enable : provides an output enable function to buf fers f0f7 from the output registers. active-low (l)
philips semiconductors product specification PLUS405-37/-45 programmable logic sequencers (16 64 8) 1996 nov 12 4 truth table 1, 2, 3, 4, 5, 6, 7 option v cc init oe i10 i11 i12 ck j k q p q f f h * * * x x x h/l h/l q f l +10v x x x x q p l l l +10v x x x x q p h h l x +10v x x x l q f l l x +10v x x x h q f h l x x +10v x x x q p q f q p l x x x x x x q p q f q f h x x * x x x q p q f hi-z +5v x +10v x x x x q p l l x +10v x x x x q p h h x x +10v x x x l q f l x x +10v x x x h q f h l x x +10v x x x q p q f q p l x x x x x x q p q f q f l x x x l l q p q f q f l x x x l h l l l l x x x h l h h h l x x x h h q p q f q f x x x x x x x x h h notes: 1. positive logic: s/r (or j/k) = t 0 + t 1 + t 2 + . . . t 63 t n = (c0, c1) (i0, i1, i2, . . .) (p0, p1, . . . p7) 2. either initialization (active-high) or output enable (active-low) are available, but not both. the desired function is a user-programmable option. 3. denotes transition from low-to-high level. 4. * = h or l or +10v 5. x = don't care (< 5.5v) 6. h/l implies that either a high or a low can occur , depending upon user-programmed selection (each state and output register individually programmable). 7. when using the f n pins as inputs to the state and output registers in diagnostic mode, the f buf fers are 3-stated and the indicated levels on the output pins are forced by the user . virgin state a factory-shipped virgin device contains all fusible links intact, such that: 1. init/oe is set to init . in order to use the init function, the user must select either the preset or the reset option for each flip-flop. note that regardless of the user-programmed initialization, or even if the init function is not used, all registers are preset to a1o by the power-up procedure. 2. all transition terms are inactive (0). 3. all s/r (or j/k) flip-flop inputs are disabled (0). 4. the device can be clocked via a test array preprogrammed with a standard test pattern. 5. clock 2 is inactive. logic function 0 1 0 0 0 1 state register s r s n + 1 present state a ? b ? c ? . . . next state q2 q1 q0 set q 0 : j 0 = (q 2 ? q 1 ? q 0 ) ? a ? b ? c . . . k 0 = 0 reset q 1 : j 1 = 0 k 1 = (q 3 ? q 2 ? q 1 ? q 0 ) ? a ? b ? c . . . hold q 2 : j 2 = 0 k 2 = 0 1 0 q3 reset q 3 : j 3 = (q 3 ? q 2 ? q 1 ? q 0 ) ? a ? b ? c . . . k 3 = (q 3 ? q 2 ? q 1 ? q 0 ) ? a ? b ? c . . . sp00231
philips semiconductors product specification PLUS405-37/-45 programmable logic sequencers (16 64 8) 1996 nov 12 5 functional diagram p63 p0 15 i x2 i/clk j k p r q (4) j k p r q (4) j k p r q (4) j k p r q (4) 4 f ck f 4 4 init/oe 4 4 4 4 4 4 4 sp00252
philips semiconductors product specification PLUS405-37/-45 programmable logic sequencers (16 64 8) 1996 nov 12 6 logic diagram detail a detail b detail c detail d 9 8 7 6 5 4 3 2 1 27 26 25 24 23 22 21 20 19 18 17 16 15 13 12 11 10 i0 i1 i2 i3 i4 i6 i7 i8 i9 i10 i11 i12 i13 i14 i15 i5/clk init/oe f0 f1 f2 f3 f4 f5 f6 f7 clk note: denotes a programmable fuse location. sp00253
philips semiconductors product specification PLUS405-37/-45 programmable logic sequencers (16 64 8) 1996 nov 12 7 details for registers for plus405 state registers j k q p r clk to init line to and array detail b 19 init/oe detail a p s output registers j k q p r clk to init line detail c f n from pin 1 clk from pin 4 (i5/clk) detail d sp00254 complement array detail p63 p62 p2 p1 p0 a b c0 d e c1 c1 c0 to or array sp00255 the complement array is a special sequencer feature that is often used for detecting illegal states. it is also ideal for generating if-then-else logic statements with a minimum number of product terms. the concept is deceptively simple. if you subscribe to the theory that the expressions (/a * /b * /c) and (a + b + c ) are equivalent, you will begin to see the value of this single term nor array . the complement array is a single or gate with inputs from the and array . the output of the complement array is inverted and fed back to the and array (nor). the output of the array will be low if any one or more of the and terms connected to it are active (high). if, however , all the connected terms are inactive (low), which is a classic unknown state, the output of the complement array will be high. consider the product t erms a, b and d that represent defined states. they are also connected to the input of the complement array . when the condition (not a and not b and not d) exists, the complement array will detect this and propagate an active-high signal to the and array . this signal can be connected to product t erm e, which could be used in turn to reset the state machine to a known state. without the complement array , one would have to generate product terms for all unknown or illegal states. with very complex state machines, this approach can be prohibitive, both in terms of time and wasted resources. note that the plus405 has 2 complement arrays which allow the user to design 2 independent complement functions. this is particularly useful if 2 independent state machines have been implemented on one device. note that use of the complement array adds an additional delay path through the device. please refer to the ac electrical characteristics for details.
philips semiconductors product specification PLUS405-37/-45 programmable logic sequencers (16 64 8) 1996 nov 12 8 absolute maximum ratings 1 symbol parameter ratings unit v cc supply voltage +7 v dc v in input voltage +5.5 v dc v out output voltage +5.5 v dc i in input currents 30 to +30 ma i out output currents +100 ma t amb operating temperature range 0 to +75 c t sstg storage temperature range 65 to +150 c notes: 1. stresses above those listed may cause malfunction or permanent damage to the device. this is a stress rating only . functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. thermal ratings temperature maximum junction 150 c maximum ambient 75 c allowable thermal rise ambient to junction 75 c dc electrical characteristics 0 c t amb +75 c, 4.75v v cc 5.25v limits symbol parameter test conditions min typ 1 max unit input voltage 2 v ih high v cc = max 2.0 v v il low v cc = min 0.8 v v ic clamp 3 v cc = min, i in = 12ma 0.8 1.2 v output voltage 2 v oh high v cc = min, i oh = 2ma 2.4 v v ol low v cc = min, i ol = 9.6ma 0.35 0.45 v input current i ih high v cc = max, v in = v cc <1 30 m a i il low v cc = max, v in = 0.45v 20 250 m a output current i o(off) hi-z state v cc = max, v out = 2.7v 1 40 m a v cc = max, v out = 0.45v 1 40 m a i os short circuit 3, 4 v out = 0v 15 70 ma i cc v cc supply current 5 v cc = max 190 225 ma capacitance c in input v cc = 5.0v, v in = 2.0v 8 pf c out output v cc = 5.0v, v out = 2.0v 10 pf notes: 1. all typical values are at v cc = 5v. t amb = +25 c. 2. all voltage values are with respect to network ground terminal. 3. test one at a time. 4. duration of short-circuit should not exceed one second. 5. i cc is measured with the init/oe input grounded, all other inputs at 4.5v and the outputs open.
philips semiconductors product specification PLUS405-37/-45 programmable logic sequencers (16 64 8) 1996 nov 12 9 ac electrical characteristics r 1 = 470 w , r 2 = 1k w , c l = 30pf, 0 c t amb +75 c, 4.75v v cc 5.25v limits symbol parameter from to PLUS405-37 plus405-45 unit min typ 1 max min typ 1 max pulse width t ckh1 clock high; clk1 (pin 1) ck+ ck 10 8 8.5 7 ns t ckl1 clock low; clk1 (pin 1) ck ck+ 10 8 8.5 7 ns t ckp1 clk1 period ck+ ck+ 20 16 17 14 ns t ckh2 clock high; clk2 (pin 4) ck+ ck 10 8 10 8 ns t ckl2 clock low; clk2 (pin 4) ck ck+ 10 8 10 8 ns t ckp2 clk2 period ck+ ck+ 20 16 20 16 ns t inith initialization pulse init init+ 15 10 15 8 ns setup time t is1 input input ck+ 15 12 12 10 ns t is2 input (through complement array) input ck+ 25 20 22 18 ns t vs power-on preset v cc + ck 0 10 0 10 ns t vck clock resume (after initialization) init ck 0 5 0 5 ns t nvck clock lockout (before initialization) ck init 15 5 15 5 ns hold time t ih input ck+ input 0 5 0 5 ns propagation delay t cko1 clock1 (pin 1) ck1+ output 10 12 8 10 ns t cko2 clock2 (pin 4) ck2+ output 12 15 10 12 ns t oe 2 output enable oe output 12 15 12 15 ns t od 2 output disable oe+ output + 12 15 12 15 ns t init initialization init+ output + 15 20 15 20 ns t ppr power-on preset v cc + output + 0 10 0 10 ns notes on following page
philips semiconductors product specification PLUS405-37/-45 programmable logic sequencers (16 64 8) 1996 nov 12 10 ac electrical characteristics (continued) r 1 = 470 w , r 2 = 1k w , c l = 30pf, 0 c t amb +75 c, 4.75v v cc 5.25v limits symbol parameter from to PLUS405-37 plus405-45 unit min typ 1 max min typ 1 max frequency of operation f max1 clk1; without complement array 1 t is1 t cko1 input output 37.0 45.5 45.5 55.6 mhz f max2 clk2; without complement array 1 t is1 t cko2 input output 33.0 41.7 41.7 50.0 mhz f max3 clk1; with complement array 1 t is2 t cko1 input thru complement array output 27.0 33.3 31.3 38.5 mhz f max4 clk2; with complement array 1 t is2 t cko2 input thru complement array output 25.0 31.3 29.4 35.7 mhz f max5 internal feedback without complement array (clk1 or clk2) 1 t ckl t ckh register output register intput 50.0 62.5 58.8 72.4 mhz f max6 internal feedback with complement array (clk1 or clk2) 1 t is2 register output thru complement array register intput 40.0 50.0 45.5 55.6 mhz f clk minimum guaranteed clock frequency ck + ck + 50.0 62.5 58.8 72.4 mhz notes: 1. all typical values are at v cc = 5v, t amb = +25 c. 2. for 3-state output; output enable times are tested with c l = 30pf to the 1.5v level, and s 1 is open for high-impedance to high tests and closed for high-impedance to low tests. output disable times are tested with c l = 5pf . high-to-high impedance tests are made to an output voltage of v t = (v oh 0.5v) with s 1 open, and low-to-high impedance tests are made to the v t = (v ol + 0.5v) level with s 1 closed. 3. all propagation delays and setup times are measured and specified under worst case conditions. test load circuit +5v c l r 1 r 2 s 1 gnd f7 f0 inputs i0 i15 ck outputs c 2 c 1 dut note: c 1 and c 2 are to bypass v cc to gnd. v cc init/oe sp00256 voltage waveforms 90% 10% 2.5ns 2.5ns 2.5ns 2.5ns 90% 10% +3.0v +3.0v 0v 0v t r t f measurements: all circuit delays are measured at the +1.5v level of inputs and outputs, unless otherwise specified. input pulses sp00007
philips semiconductors product specification PLUS405-37/-45 programmable logic sequencers (16 64 8) 1996 nov 12 11 timing diagrams t cko sequential mode 1.5v 1.5v 1.5v 1.5v 1.5v 1.5v 1.5v 1.5v 1.5v i0 i15 f0 f7 clk oe +3v +3v +3v 0v 0v 0v v oh v ol t ih t is t ckl t ckh t is f max t od t oe t ckp sp00257 t nvck t vck t cko asynchronous initialization ????? ????? ????? ????? i0 i15 f0 f7 clk init 1.5v 1.5v 1.5v 1.5v 1.5v 1.5v 1.5v 1.5v 1.5v 1.5v +3v +3v +3v 0v 0v 0v v oh v ol t ckh t ckl t is t init t inith t cko sp00258 f max t cko t ih ????? ????? ????? ????? ????? power-on preset 2.5v 1.5v t ppr v cc f0 f7 clk i0 i15 +5v 0v v oh v ol +3v 0v +3v 0v 1.5v 1.5v 1.5v 1.5v 1.5v 1.5v t is t ckh t vs [f n ] = 1 [f n ] + 1 sp00259a
philips semiconductors product specification PLUS405-37/-45 programmable logic sequencers (16 64 8) 1996 nov 12 12 timing diagrams (continued) t cko t ih diagnostic mode state register outputs f0 f7 1.5v t is v oh v ol +3v 0v 1.5v 1.5v 1.5v 8.0v 8.0v 1.5v 1.5v 1.5v 1.5v 0v +10v +3v 0v +3v 0v v oh v ol i12 i0 i11, i13 i15 clk q0 q7 oe t ckh internal state reg. (p s ) t sre t srd (f n ) (f n+1 ) (f n+1 ) (n s ) (n s ) sp00260 t cko t rh t rjs diagnostic mode state register input jam 8.0v 8.0v i11 f0 f7 (inputs) +10v +3v 0v +3v 0v +3v 0v v oh v ol t rjh 1.5v 1.5v 1.5v 1.5v t is t ckh (forced d in ) (d in ) clk q p state reg. ( ) sp00261 diagnostic modeeoutput register input jam ( ) q f state reg. t cko t rh t rjs 8.0v 8.0v i10 f0 f7 (inputs) +10v +3v 0v +3v 0v +3v 0v v oh v ol t rjh 1.5v 1.5v 1.5v 1.5v t is t ckh (forced d in ) (d in ) clk1/2 sp00243
philips semiconductors product specification PLUS405-37/-45 programmable logic sequencers (16 64 8) 1996 nov 12 13 timing definitions symbol parameter t ckh1, 2 width of input clock pulse. t ckp1, 2 minimum guaranteed clock period. t is1 required delay between beginning of valid input and positive transition of clock. t cko1, 2 delay between positive transition of clock and when outputs become valid (with init/oe low). t ppr delay between v cc (after poweron) and when outputs become preset at a1o. t is2 required delay between beginning of valid input and positive transition of clock, when using optional complement array (two passes necessary through the and array). t rjh required delay between positive transition of clock, and return of input i10, i1 1 or i12 from diagnostic mode (10v). f max1, 2 minimum guaranteed operating frequency; input to output (clk1 and clk2). f max3, 4 minimum guaranteed operating frequency; input through complement array , to output (clk1 and clk2). f max5 minimum guaranteed internal operating frequency; with internal feedback from state register to state register . f max6 minimum guaranteed internal operating frequency with complement array , with internal feedback from state register through complement array, to state register. f clk minimum guaranteed clock frequency (register toggle frequency). t ckl1, 2 interval between clock pulses. t ih required delay between positive transition of clock and end of valid input data. t oe delay between beginning of output enable low and when outputs become valid. t sre delay between input i12 transition to diagnostic mode and when the outputs reflect the contents of the state register . t rjs required delay between inputs i1 1, i10 or i12 transition to diagnostic mode (10v), and when the output pins become available as inputs. t nvck required delay between the negative transition of the clock and the negative transition of the asynchronous initialization to guarantee that the clock edge is not detected as a valid negative transition. t inith width of initialization input pulse. t vs required delay between v cc (after poweron) and negative transition of clock preceding first reliable clock pulse. t od delay between beginning of output enable high and when outputs are in the offstate. t init delay between positive transition of initialization and when outputs become valid. t srd delay between input i12 transition to logic mode and when the outputs reflect the contents of the output register . t rh required delay between positive transition of clock and end of valid input data when jamming data into state or output registers in diagnostic mode. t vck required delay between negative transition of asynchronous initialization and negative transition of clock preceding first reliable clock pulse.
philips semiconductors product specification PLUS405-37/-45 programmable logic sequencers (16 64 8) 1996 nov 12 14 logic programming the PLUS405-37/-45 is fully supported by industry standard (jedec compatible) pld cad tools, including philips semiconductors snap design software packages. abel ? and cupl ? design software packages also support the PLUS405-37/-45 architecture. all packages allow boolean and state equation entry formats. snap , abel and cupl also accept, as input, schematic capture format. PLUS405-37/-45 logic designs can also be generated using the program table entry format, which is detailed on the following pages. this program table entry format is supported by snap only . t o implement the desired logic functions, each logic variable (i, b, p , s, t , etc.) from the logic equations is assigned a symbol. true, complement, preset, reset, output enable, inactive, etc., symbols are defined below. initialization/oe option (init/oe ) option code l oe option code h initialization 1 init (always enabled) e = 1 init/oe init = 0 e init/oe (initialization disabled) sp00265 programming the plus405: the plus405 has a power-up preset feature. this feature insures that the device will power-up in a known state with all register elements (state and output register) at logic high (h). when programming the device it is important to realize this is the initial state of the device. you must provide a next state jump if you do not wish to use all highs (h) as the present state. initialization option (init) code o action indeterminate 4 code action code action preset h reset l code action indeterminate 4 init p r init p r init p r init p r init p r sp00266 aando array (i), (p) code o state inactive 1, 2 code state code state code state i, p h i, p l don't care t n i, p i, p t n i, p t n i, p t n i, p t n i, p i, p i, p i, p i, p i, p i, p i, p sp00267 notes are on next page. abel is a trademark of data i/o corp. cupl is a trademark of logical devices, inc.
philips semiconductors product specification PLUS405-37/-45 programmable logic sequencers (16 64 8) 1996 nov 12 15 aoro array j-k function (n), (f) code action code action set h reset l n, f n, f t n j q k code action toggle 1, 6 o n, f n, f t n j q k n, f n, f t n j q k n, f n, f t n j q k code action no change sp00268 acomplemento array (c) code o action inactive 1, 3 code action code action code action generate a propagate ? transparent t n c c t n c t n c t n c c c c sp00269 clock option (clk1/clk2) option code l clk1 only 1 clk2 clk1 option code h clk1 and clk2 5 clk2 clk1 sp00270 notes: 1. this is the initial unprogrammed state of all links. 2. any gate t n will be unconditionally inhibited if any one of its i or p link pairs is left intact. 3. t o prevent oscillations, this state is not allowed for c link pairs coupled to active gates t n . 4. these states are not allowed when using initializa tion option. 5. input buf fer i5 must be deleted from the and array (i.e., all fuse locations adon't careo) when using second clock option. 6. a single product term cannot drive more than 8 registers by itself when used in t oggle mode. programming/software support refer to section 9 (development software) and section 10 (third-party programmer/ software support) of this data handbook for additional information.
philips semiconductors product specification PLUS405-37/-45 programmable logic sequencers (16 64 8) 1996 nov 12 16 plus405 program table notes: 1. the device is shipped with all links initially intact. thus, a background of a0o for all terms, and an aho for the in/e and h for the clock option, exists in the table, shown blank instead for clarity. 2. unused cn im, and ps bits are normally programmed don't care (e). 3. unused transition terms can be left blank for future code modification, or programmed as (e) for maximum speed. inactive or toggle n7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 pin no. pin labels 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 5 1 6 1 7 1 8 c1 c0 comp. array input (im) and present state (ps) next state (ns) or output (fr) clock 1/2 initialization/output enable customer name philips device # customer symbolized p art # cf (xxxx) rev date program table i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 p7 p6 p5 p4 p3 p2 p1 p0 n6 n5 n4 n3 n2 n1 n0 f7 f6 f5 f4 f3 f2 f1 f0 options or and init oe clk1 only clk1 and 2 h l l h init/oe clk1/ clk2 ns, fr set reset no change l h 0 inactive generate propagate transparent 0 a ? cn inactive i, p i, p don't care 0 h im, ps l sp00263
philips semiconductors product specification PLUS405-37/-45 programmable logic sequencers (16 64 8) 1996 nov 12 17 snap resource summary designations and p63 p0 15 i x2 i/clk j k p r q (4) j k p r q (4) j k p r q (4) j k p r q (4) 4 f ck f 4 4 init/oe 4 4 4 4 4 4 4 din405 nin405 jkff405 ck405 ck405 out405 out405 nor din405 nin405 sp00264
philips semiconductors product specification PLUS405-37/-45 programmable logic sequencers (16 64 8) 1996 nov 12 18 dip28: plastic dual in-line package; 28 leads (600 mil); long body sot117-2
philips semiconductors product specification PLUS405-37/-45 programmable logic sequencers (16 64 8) 1996 nov 12 19 plcc28: plastic leaded chip carrer; 28 leads; pedestal sot261-3
philips semiconductors product specification PLUS405-37/-45 programmable logic sequencers (16 64 8) 1996 nov 12 20 philips semiconductors and philips electronics north america corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. life support applications philips semiconductors and philips electronics north america corporation products are not designed for use in life support appliances, devices, or systems where malfunction of a philips semiconductors and philips electronics north america corporation product can reasonably be expected to result in a personal injury . philips semiconductors and philips electronics north america corporation customers using or selling philips semiconductors and philips electronics north america corporation products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors and philips electronics north america corporation for any damages resulting from such improper use or sale. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 definitions data sheet identification product status definition objective specification preliminary specification product specification formative or in design preproduction product full production this data sheet contains the design target or goal specifications for product development. specifications may change in any manner without notice. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. philips semiconductors and philips electronics north america corporation register eligible circuits under the semiconductor chip protection act. ? copyright philips electronics north america corporation 1996 all rights reserved. printed in u.s.a.

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